This invention relates to integrated semiconductor devices, and more particularly to an integrated bipolar transistor having a self-aligned polysilicon base contact.
Semiconductor integrated circuits have substantially increased in density in the past decade. However, there is an increasing demand for greater complexities, higher switching speeds and smaller devices for new applications such as microprocessors and minicomputers. As integrated circuits become more dense, a major problem is the electrical contacts to the various elements and devices in the integrated circuit. Large numbers of contacts are necessary for making the requisite device connections. These contacts must be isolated from one another and from other devices, and must be properly aligned.
Recent attempts to provide electrical contacts for integrated devices have employed highly doped polycrystalline silicon (hereinafter, polysilicon) as the conductive contact layer. For example, polysilicon contact techniques have been employed to form the base contacts of high density integrated bipolar transistors. However, the currently known polysilicon base contact process has not been completely satisfactory, as described below.
A state of the art process for forming an integrated bipolar transistor having a self-aligned polysilicon base contact begins with a semiconductor substrate having an isolated collector region formed therein. A polysilicon layer is deposited on the semiconductor substrate and a silicon nitride passivating layer is formed on the polysilicon layer. An opening is formed in the polysilicon and silicon nitride layers, over the collector region, through which the base is implanted. A thick conformal layer of chemical vapor deposited (CVD) silicon dioxide is then deposited on the polysilicon layer including the opening therein. This silicon dioxide layer is reactive ion etched (RIE) in an ambient of CF.sub.4 or CF.sub.4 +H.sub.2 to remove the horizontal portion thereof over the polysilicon layer and within the opening, while leaving a vertical silicon dioxide sidewall on the wall of the opening. An emitter is then implanted through the opening in the silicon dioxide sidewall, and a contact to the emitter is made.
While theoretically providing a bipolar transistor having a self-aligned polysilicon base contact, the above state of the art process has been difficult to implement because the RIE step requires two etch rate ratios which are mutually unattainable with currently known RIE techniques. More particularly, the RIE step requires a high etch rate ratio (ERR) of silicon dioxide to silicon so that the emitter region is not thinned when the silicon dioxide layer is reactive ion etched. Emitter region thinning, (and the resultant thinning of the later implanted base region) decreases transistor gain and provides excessive parameter variation from transistor to transistor.
On the other hand, the RIE step requires a high ERR of silicon dioxide to silicon nitride, so that the silicon nitride passivation layer on top of the polysilicon layer is not etched. Silicon nitride passivation layer etching causes thinning of the passivation layer and may even create shorts or pinholes therein. When metal lines are subsequently run over the thinned passivation layer, the excessive capacitance of the thinned layer degrades the speed of, and creates cross talk among, the metal lines. Moreover, if a short occurs between the polysilicon base contact and the metal lines due to a pinhole in the thinned silicon nitride passivation layer, the integrated circuit will not be usable.
Thus, the state of the art polysilicon base contact process requires an RIE technique having a high ERR of silicon dioxide to silicon and a high ERR of silicon dioxide to silicon nitride. A high ERR of silicon dioxide to silicon nitride itself is difficult to attain using currently known RIE techniques. Moreover, no currently known reactive ion etching technique satisfies the simultaneous high ERR requirement. Thus, known RIE ambients (i.e., CF.sub.4, CF.sub.4 +H.sub.2, Ar+Cl.sub.2, SF.sub.6 +Cl.sub.2, etc.) present a compromise which results in etching into the emitter, etching into the silicon nitride passivation layer, or both.